In recent years, as the speed of SoCs (Systems on Chip) has been increased, problematic electromagnetic radiation (EMI: Electromagnetic Interference) has become significant in LSIs (Large Scale Integrations) or digital household electrical appliances. The SSC-PLL is a technique by which small modulation is performed with respect to the frequency (input frequency) of a reference clock signal in an LSI to spread the spectrum of an output clock signal, thereby reducing the peak value of EMI. The SSC-PLL can be implemented with low cost, and in addition, has a high peak value reducing effect, and therefore, is considered as a promising solution to the EMI problem. As a spread spectrum modulation technique, a triangular wave modulation technique, which has a high peak reducing effect, is often used. A spread spectrum modulation frequency is typically several tens of KHz.
On the other hand, in the field of high-speed interfaces, such as an in-car IF (Interface), LVDS (Low Voltage Differential Signaling), and HDMI (High-Definition Multimedia Interface), as the functionality and performance of digital household electrical appliances have been increased, the operating frequency has had a wider range. For example, as an input frequency, the in-car IF requires 13.5 MHz to 81 MHz, LVDS requires 20 MHz to 160 MHz, and HDMI requires 27 MHz to 225 MHz. Therefore, the SSC-PLL needs to support a wide range of frequencies.
Referring to FIG. 15, in the SSC-PLL, output jitter caused by quantization noise increases with an increase in loop bandwidth. On the other hand, output distortion caused by spread spectrum modulation increases with a decrease in loop bandwidth. As the output distortion becomes larger, the EMI peak value reducing effect becomes smaller. Therefore, in the SSC-PLL, it is desirable to fix the loop bandwidth to an optimal value which reduces both the jitter and the distortion (an optimal point shown in FIG. 15). However, since characteristics of the jitter and the distortion vary depending on the input frequency, the optimal value of the loop bandwidth also varies (see FIG. 15). Therefore, if the loop bandwidth is fixed, then when the input frequency varies over a wide range, the jitter or the distortion is likely to increase.
To solve this problem, there is a technique in which the loop bandwidth is set to an optimal value by nonlinearly changing the gain of a VCO (Voltage Controlled Oscillator) included in the SSC-PLL which would otherwise linearly change with respect to a control voltage, to follow a change in the input frequency (see, for example, Patent Document 1).    Patent Document 1: U.S. Pat. No. 6,980,581